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| NID9N05CL Power MOSFET 9.0 A, 52 V, N-Channel, Logic Level, Clamped MOSFET w/ESD Protection in a DPAK Package http://onsemi.com Benefits * High Energy Capability for Inductive Loads * Low Switching Noise Generation Features VDSS (Clamped) 52 V RDS(ON) TYP 90 mW ID MAX (Limited) 9.0 A Drain (Pins 2, 4) * * * * * * Diode Clamp Between Gate and Source ESD Protection - HBM 5000 V Active Over-Voltage Gate to Drain Clamp Scalable to Lower or Higher RDS(on) Internal Series Gate Resistance Pb-Free Packages are Available Gate (Pin 1) RG Overvoltage Protection MPWR Applications ESD Protection * Automotive and Industrial Markets: Solenoid Drivers, Lamp Drivers, Small Motor Drivers MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Rating Drain-to-Source Voltage Internally Clamped Gate-to-Source Voltage - Continuous Drain Current - Continuous @ TA = 25C Drain Current - Single Pulse (tp = 10 ms) Total Power Dissipation @ TA = 25C Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 125C (VDD = 50 V, ID(pk) = 1.5 A, VGS = 10 V, RG = 25 W) Thermal Resistance, Junction-to-Case Junction-to-Ambient (Note 1) Junction-to-Ambient (Note 2) Maximum Lead Temperature for Soldering Purposes, 1/8 from Case for 10 seconds Symbol VDSS VGS ID IDM PD TJ, Tstg EAS Value 52-59 15 9.0 35 28.8 -55 to 175 160 Unit V V A W C mJ DPAK CASE 369C STYLE 2 Y WW D9N05CL G 1 2 3 YWW D9N 05CLG Source (Pin 3) MARKING DIAGRAM 4 RqJC RqJA RqJA TL 5.2 72 100 260 C/W = Year = Work Week = Device Code = Pb-Free Package 1 2 3 4 = Gate = Drain = Source = Drain ORDERING INFORMATION C Device NID9N05CLT4 NID9N05CLT4G NID9N05CL NID9N05CLG Package DPAK DPAK (Pb-Free) DPAK DPAK (Pb-Free) Shipping 2500/Tape & Reel 2500/Tape & Reel 75 Units/Rail 75 Units/Rail Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. When surface mounted to a FR4 board using 1 pad size, (Cu area 1.127 in2). 2. When surface mounted to a FR4 board using minimum recommended pad size, (Cu area 0.412 in2). For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. (c) Semiconductor Components Industries, LLC, 2006 1 April, 2006 - Rev. 7 Publication Order Number: NID9N05CL/D NID9N05CL ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (Note 3) (VGS = 0 V, ID = 1.0 mA, TJ = 25C) (VGS = 0 V, ID = 1.0 mA, TJ = -40C to 125C) Temperature Coefficient (Negative) Zero Gate Voltage Drain Current (VDS = 40 V, VGS = 0 V) (VDS = 40 V, VGS = 0 V, TJ = 125C) Gate-Body Leakage Current (VGS = 8 V, VDS = 0 V) (VGS = 14 V, VDS = 0 V) ON CHARACTERISTICS (Note 3) Gate Threshold Voltage (Note 3) (VDS = VGS, ID = 100 mA) Threshold Temperature Coefficient (Negative) Static Drain-to-Source On-Resistance (Note 3) (VGS = 4.0 V, ID = 1.5 A) (VGS = 3.5 V, ID = 0.6 A) (VGS = 3.0 V, ID = 0.2 A) (VGS = 12 V, ID = 9.0 A) (VGS = 12 V, ID = 12 A) Forward Transconductance (Note 3) (VDS = 15 V, ID = 9.0 A) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance Input Capacitance Output Capacitance Transfer Capacitance (VDS = 25 V, VGS = 0 V, f = 10 kHz) (VDS = 40 V, VGS = 0 V, f = 10 kHz) Ciss Coss Crss Ciss Coss Crss - - - - - - 155 60 25 175 70 30 250 100 40 - - - pF pF VGS(th) 1.3 - RDS(on) - - - 70 67 gFS - 153 175 - 90 95 24 181 364 1210 - - - Mhos 1.75 -4.5 2.5 - V mV/C mW V(BR)DSS 52 50.8 - IDSS - - IGSS - - - 22 - - 10 25 10 - mA 55 54 -10 59 59.5 - V V mV/C mA Symbol Min Typ Max Unit 3. Pulse Test: Pulse Width 300 ms, Duty Cycle 2%. 4. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 2 NID9N05CL ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic SWITCHING CHARACTERISTICS (Note 4) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Gate Charge (VGS = 4.5 V, VDS = 40 V, ID = 9.0 A) (Note 3) Gate Charge (VGS = 4.5 V, VDS = 15 V, ID = 1.5 A) (Note 3) SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (IS = 4.5 A, VGS = 0 V) (Note 3) (IS = 4.0 A, VGS = 0 V) (IS = 4.5 A, VGS = 0 V, TJ = 125C) (IS = 4.5 A, VGS = 0 V, dIs/dt = 100 A/ms) (Note 3) Reverse Recovery Stored Charge ESD CHARACTERISTICS Electro-Static Discharge Capability Human Body Model (HBM) Machine Model (MM) ESD 5000 500 - - - - V VSD - - - - - - - 0.86 0.845 0.725 700 200 500 6.5 1.2 - - - - - - mC V (VGS = 10 V, VDD = 15 V, ID = 1.5 A, RG = 50 W) (VGS = 10 V, VDD = 15 V, ID = 1.5 A, RG = 2 kW) (VGS = 10 V, VDD = 40 V, ID = 9.0 A, RG = 9.0 W) td(on) tr td(off) tf td(on) tr td(off) tf td(on) tr td(off) tf QT Q1 Q2 QT Q1 Q2 - - - - - - - - - - - - - - - - - - 130 500 1300 1150 200 500 2500 1800 120 275 1600 1100 4.5 1.2 2.7 3.6 1.0 2.0 200 750 2000 1850 - - - - - - - - 7.0 - - - - - nC nC ns ns ns Symbol Min Typ Max Unit Reverse Recovery Time trr ta tb QRR ns 3. Pulse Test: Pulse Width 300 ms, Duty Cycle 2%. 4. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 3 NID9N05CL 18 ID, DRAIN CURRENT (AMPS) 8V 6.5 V ID, DRAIN CURRENT (AMPS) 16 14 12 10 8 6 4 2 0 0 1 2 3 4 5 6 7 8 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 3.2 V 4.6 V 4.2 V 4V 3.8 V 3.4 V 2.8 V VGS = 10 V 6V TJ = 25C 5V 16 14 12 10 8 6 4 2 0 1 2 3 4 5 6 7 8 9 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) VDS 10 V TJ = -55C TJ = 25C TJ = 100C 18 Figure 1. On-Region Characteristics RDS(on), DRAIN-TO-SOURCE RESISTANCE (W) RDS(on), DRAIN-TO-SOURCE RESISTANCE (W) Figure 2. Transfer Characteristics 0.5 ID = 4.5 A TJ = 25C 0.4 0.35 VGS = 4 V 0.3 0.25 0.2 0.15 0.1 0.05 0 0 2 4 6 8 10 12 14 16 18 VGS = 12 V TJ = 25C 0.4 0.3 0.2 0.1 0 2 4 6 8 10 12 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) ID, DRAIN CURRENT (AMPS) Figure 3. On-Resistance versus Gate-to-Source Voltage RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) 2.5 ID = 9 A VGS = 12 V 2 100,000 IDSS, LEAKAGE (nA) 1,000,000 Figure 4. On-Resistance versus Drain Current and Gate Voltage VGS = 0 V 1.5 TJ = 150C TJ = 100C 1000 10,000 1 0.5 -50 -25 100 0 25 50 75 100 125 150 175 20 25 30 35 40 45 50 TJ, JUNCTION TEMPERATURE (C) VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-to-Source Leakage Current versus Voltage http://onsemi.com 4 NID9N05CL 500 Frequency = 10 kHz C, CAPACITANCE (pF) 400 TJ = 25C VGS = 0 V 300 200 Coss Crss 0 0 10 Ciss 100 20 30 40 50 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) Figure 7. Capacitance Variation VGS , GATE-TO-SOURCE VOLTAGE (VOLTS) 5 QT 4 Qgs Qgd VGS 50 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 10,000 VDD = 40 V ID = 9 A VGS = 10 V t, TIME (ns) td(off) tf tr 40 3 30 1000 2 VDS ID = 9 A TJ = 25C 20 1 0 0 1 10 0 td(on) 100 1 10 RG, GATE RESISTANCE (OHMS) 100 2 3 4 Qg, TOTAL GATE CHARGE (nC) 5 Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS 10 IS, SOURCE CURRENT (AMPS) VGS = 0 V TJ = 25C 8 6 4 2 0 0.4 0.6 0.8 1.0 VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS) 1.2 Figure 10. Diode Forward Voltage versus Current http://onsemi.com 5 NID9N05CL SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance - General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 ms. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RqJC). A Power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For 100 I D, DRAIN CURRENT (AMPS) VGS = 12 V SINGLE PULSE TC = 25C 10 1 ms 10 ms 10 ms 100 ms reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. 1 dc 0.1 0.1 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1 10 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 100 r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED) Figure 11. Maximum Rated Forward Biased Safe Operating Area 1.0 D = 0.5 0.2 0.1 0.1 0.05 0.01 SINGLE PULSE 0.01 0.00001 0.0001 0.001 t1 t2 DUTY CYCLE, D = t1/t2 0.01 t, TIME (s) 0.1 P(pk) RqJC(t) = r(t) RqJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RqJC(t) 1 10 Figure 12. Thermal Response http://onsemi.com 6 NID9N05CL PACKAGE DIMENSIONS DPAK CASE 369C ISSUE O -T- B V R 4 SEATING PLANE C E NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.180 BSC 0.034 0.040 0.018 0.023 0.102 0.114 0.090 BSC 0.180 0.215 0.025 0.040 0.020 --- 0.035 0.050 0.155 --- MILLIMETERS MIN MAX 5.97 6.22 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 4.58 BSC 0.87 1.01 0.46 0.58 2.60 2.89 2.29 BSC 4.57 5.45 0.63 1.01 0.51 --- 0.89 1.27 3.93 --- A S 1 2 3 Z U K F L D G 2 PL J H 0.13 (0.005) M T DIM A B C D E F G H J K L R S U V Z STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN SOLDERING FOOTPRINT* 6.20 0.244 2.58 0.101 5.80 0.228 1.6 0.063 6.172 0.243 3.0 0.118 SCALE 3:1 mm inches *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 61312, Phoenix, Arizona 85082-1312 USA Phone: 480-829-7710 or 800-344-3860 Toll Free USA/Canada Fax: 480-829-7709 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Phone: 81-3-5773-3850 ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. http://onsemi.com 7 NID9N05CL/D |
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